Introduction

This document gives some details about the hardware configuration of the Smaky 400 board. The three main components of the board are :

• The main CPU (usually, a QFP MC68LC040 running at 33 MHz).
• The MC68360 (also called QUICC by Motorola).
• The QSpan PCI to host bridge. The bus on the main CPU side is called Q-bus by Tundra.

You definitely need the MC68360 User's Manual and the QSpan User's Manual (both are available in PDF format on the web or as printed material at Motorola and Tundra's) in order to properly initialise and set up the Smaky 400 board.

Resource map

The Smaky 400 board does not have a fixed resource address map. The address of each peripheral can be defined thanks to the 68360 SIM, which is responsible for address decoding. It generates the /CSx signals which are routed as following :

/CS0	Boot chip select, not used, available on expansion connector.
/CS1	Free chip select, not used, available on expansion connector.
/RAS2	Row Address Strobe for DRAM bank 0.
/RAS3	Row Address Strobe for DRAM bank 1.
/CS4	Free chip select, not used, available on expansion connector.
/CS5	Mubus chip select.
/CS6	QSpan internal register chip select.
/CS7	QSpan PCI image chip select (image selected through A31).

Boot procedure

The Smaky 400 board design does not include ROMs nor any other kind of non-volatile storage on which the main CPU could boot. Therefore, it is the host’s responsibility to set up the memory before starting the main CPU.

This set up procedure can be described as following :

1. Configure the QSpan so that the host processor can access the Q-bus, then pulse the software reset signal (register misc_ctl).
2. Set up the MBAR in the 68360 (access address is 0x0003FF00 in CPU space mode 7) with the proper mask and enable bits.
3. Set up the SYPCR in the 68360 (System Protection Control Register, 6.9.3.5) in order to disable the software watchdog; otherwise, the 68360 would be reset again in less than a second.
4. Initialise the 68360 (memory decoding, pin assignment registers, etc.) as needed. The PEPAR has to be initialised as following :
   • /IOUT2..0 map to pins 203, 202 and 199.
   • /BCLRO is an output on pin 210.
   • /BCLRI is an input on pin 207.
   • A31..28 map to address lines, not /WE0..3.
   • AMUX is output on pin 212.
   • /CAS3..2 and /CAS1..0 are output on pins 182, 183, 185 and 187.
   • /CS7 is output on pin 171.
   • /AVECO is output on pin 233.
5. Test the DRAM and set up the refresh accordingly. Memory is seen contiguously within a given bank.
6. Download the boot code for the main CPU to the DRAM and make sure it has been mapped to address 0x00000000.
7. Start the main CPU by actively driving high the PB16 output (directly connected to the /RSTI pin of the main CPU; a 1 K pull-down insures that when the 68360 is reset, /RSTI becomes active).